Different instruction issue modes have different power and performance trade-offs. Processors with logic units implementing in-order instruction issue modes issue instructions in the order they are fetched, allowing for a simple, energy efficient pipeline. While energy efficient, in-order instruction issue modes exhibit lower performance than out-of-order instruction issue modes because the in-order instruction issue modes must stall on miss events (e.g., waiting for an operand that has not been written back to an operand buffer or written to a registry file).
Processors with logic units implementing out-of-order instruction issue modes execute instructions based on their dependencies, providing higher performance by tolerating dynamic latencies. Out-of-order instruction issue modes, however, consume more energy than in-order instruction issue modes, as logic units implementing out-of-order instruction issue modes are more complex than logic units implementing in-order instruction issue modes. For instance, they must be able to perform dynamic scheduling, which consumes additional power.